1. Technical Field
The present invention relates to semiconductor circuits in general, and in particular to silicon on insulator semiconductor circuits. Still more particularly, the present invention relates to a method for controlling delays in silicon on insulator circuits.
2. Description of the Prior Art
In recent years, the predominant processing technology for integrated circuits has been the Complementary Metal Oxide Silicon (CMOS) technology using silicon as substrates. Although CMOS technology offers various advantages, such as low power consumption and stability, over other types of processing technologies, there are also several drawbacks associated with CMOS circuits, such as relatively slow speed and potential latchup problem. In light of such, a new processing technology called Silicon on Insulator (SOI) technology has emerged. Instead of using an electrically conducting substrate like the CMOS technology, SOI utilizes an insulating substrate, which provides tremendous improvements in certain circuit characteristics, such as speed and latch-up, over the CMOS technology. A detailed description of the SOI technology can be found in Weste and Eshraghian, Principles of CMOS VLSI Design: A Systems Perspective, 2nd ed., pp. 125-130, Addison Wesley (1995), the pertinent portion of which is incorporated herein by reference.
Even with the SOI technology, there is still a need for providing controlled delays in certain critical timing areas of an integrated circuit. For example, some clock or data signals may need to be delayed before entering certain parts of the integrated circuit in order to improve the overall speed performance. In the prior art, there are several ways to produce a selectively controlled delay in such paths. This disclosure describes an improved method for providing controlled delays in SOI integrated circuits.